Software Design tool-Kit for Heterogeneous Multi-Processor SoC (MPSoC)

Contact: Yongjoo Kim

High performance processors have continuously been demanded for about 50 years after the first computer emerged. To satisfy the demand, hardware functionalities had been added to processors. Unfortunately, this addition caused not only drastic increase of processor area, power consumption, NRE cost, but also the increase of design complexity. To overcome these drawbacks, several processors and DSPs which are specified to particular applications are integrated into a single chip. MPSoC is a new design paradigm that integrates several heterogeneous processors, memory systems, interfaces, and other required IP into a single processor.

MPSoC design technologies can be applied to various fields where the MPSoC systems are needed. Recently, digital convergence, bringing multimedia and communication to end-users, is leading to a new generation of integrated circuits. MPSoC is able to satisfy the constraints, such as getting high performance with low power consumption. However most domestic MPSoC researchers place too much emphasis on hardware technologies even though software technologies are as important as the hardware one.

In our laboratory, we are studying and implementing the automatic Software Development Kit(SDK) generation, customizing the tool kit to be specialized for each target processor. Developers can partition application into many tasks and assign them to each processor considering each task and processor's characteristics for effective application execution on MPSoC through the generated SDK.

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The detailed research topics are as follows.

- MPSoC compiler : Analyze parallelisms in an application and divide and assign it to the processors considering the specialty of each processor.

- SDK generation platform for MPSoC : A research for SDK platform including retargetable compiler that can cover diverse processors having application-specific instructions and architectures.

- Code generation methodology : Study a seamless code generation methodology in the heterogeneous MPSoC having various processores from conventional Von-Neumann-base processors to programmable IPs.

Our laboratory is developing base technologies for low power, high performance MPSoC by cooperating with other foremost laboratories, and implementing MPSoC H/W Resource Configuration Tool for optimizing Resource Utilization. This tool optimizes target application and manages resource for efficient processor utilization. And we are continuing a research in User-Retargetable compiler to generate optimized compiler for various systems.