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Code Generation for Reconfigurable Architectures

  • Software-based Selective Validation Techniques for Robust CGRAs against Soft Errors, Transactions on Embedded Computing Systems, VOL.15, NO.20, February 2016

  • Scalable Application Mapping for SIMD Reconfigurable Architecture, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, JSTS, 2015

  • Selective Validations for Efficient Protections on Coarse-Grained Reconfigurable Architectures, Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2013 (Acceptance rate: 19.2%)

  • Architecture Customization of On-chip Reconfigurable Accelerators, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2013

  • An Operation Scheduling Technique for Coarse Grained Reconfigurable Architectures, The 7th International Conference on Ubiquitous Information TEchnologies & Applications (CUTE 2012)

  • Exploiting both pipelining and data parallelism with SIMD reconfigurable architecture, Applied Reconfigurable Computing Symposium, 2012

  • Computer vision acceleration using coarse grained reconfigurable architecture, ASP-DAC, 2012

  • Improving performance of nested loops on reconfigurable array processors, ACM Transactions on Architecture and Code Optimization(TACO), 2012 (Acceptance rate: 26%)

  • High throughput data mapping for coarse-grained reconfigurable architectures, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2011

  • Memory Access Optimization in Compilation for Coarse Grained Reconfigurable Architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2011 (Acceptance rate: 25%)

  • I2CRF : Incremental Interconnect Customization for Embedded Reconfigurable Fabrics, Design Automation and Test in Europe (DATE), March 2011

  • Operation and Data Mapping for CGRA, ACM SIGPLAN/SIGBED Conference on Languages, Compiler and Tools for Embedded Systems (LCTES), April 2010

  • Memory-Aware Application Mapping on Coarse Grain Reconfigurable Arrays, International conference on High-Performance Embedded Architectures and Compilers (HiPEAC), Feb 2010

  • A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2009

  • SPKM: A Novel Graph Drawing based Algorithm for Application Mapping onto Coarse-Grained Reconfigurable Architectures, Asia and South Pacific Design Automation Conference(ASP-DAC), January 2008

  • Efficient Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm, Workshop on Application Specific Processors (WASP), September 2007 ( Best paper,invited for IEEE Transactions on VLSI)

  • Mapping Loops onto a Coarse-Grained Reconfigurable Architecture for High-Performance Embedded Systems, International Conference on Ubiquitous Information Technologies & Applications (ICUT), February 2007

  • Temporal Mapping for Loop Pipelining on a MIMD style Coarse-Grained Reconfigurable Architecture, International SoC Design Conference, Oct. 2006

  • A Spatial Mapping Algorithm for Heterogeneous Coarse-Grained Reconfigurable Architectures, Design Automation and Test in Europe (DATE) 2006