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Design Exploration for Optimal Embedded H/W Architectures

  • Development of Custom Digital Signal Processor for Finger Recognition Vision Application, International Conference on Ubiquitous Computing Application and Wireless Sensor Network, 2016

  • Modulo scheduler implementation for VLIW processor, SoC Design Conference (ISOCC), 2014

  • A Study of Burst Transfer Generation, The 9th KIPS International Conference on Ubiquitous Information Technologies and Applications(CUTE), 2014

  • Improving Performance of Loops on DIAM-based VLIW Architecture, Proceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems(LCTES), 2014

  • Reducing Instruction Bit-Width for Low-Power VLIW Architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2013

  • Efficient Utilization of Burst Data Transfers of DMA, IEMEK Journal of Embedded Systems and Applications 8 (5), 255-264, 2013

  • An Operation Scheduling Technique for Coarse Grained Reconfigurable Architectures, Ubiquitous Information Technologies and Applications, 2013

  • Dynamic Code Duplication with Vulnerability Awareness for Soft Error Detection on VLIW Architectures, ACM Transactions on Architecture and Code Optimization (TACO), 2013

  • Compiler and microarchitectural approaches for register file thermal management, IEEE international Symposium on Circuits and Systems(ISCAS), 2012

  • Dynamic Operands Insertion for VLIW Architecture witha Reduced Bit-width Instruction Set, IEEE International Parallel & Distributed Processing Symposium, 2012 (Acceptance rate: 20.7%)

  • Compiler-Assisted soft error correction by duplicating instructions for VLIW architecture, SASIMI, 2012

  • Operation and data mapping for CGRAs with multi-bank memory, ACM Sigplan Notices 45 (4), 17-26, 2010

  • Two Versions of Architectures for Dynamic Implied Addressing Mode, Journal of Systems Architecture (JSA), 2010

  • VLIW processor for H.264 : Integer transform and Quantization, International SoC Design Conference (ISOCC), November 2010

  • An Asip Approach for Motion Estimation Reusing Resources for H.264 Intra Prediction, International SoC Design Conference (ISOCC), November 2010

  • Implementing Dynamic Implied Addressing Mode for Multi-Output Instructions, International Conference on Compiler, Architecture and Synthesis for Embedded Systems (CASES), October 2010

  • Application-Specific Instruction Set Processor For H.264 On-Chip Encoder, International SoC Design Conference (ISOCC), 2009

  • A new addressing mode for the encoding space problem on embedded processors, 7th IEEE Symposium on Application Specific Processors (SASP), July 2009

  • Orthogonal Instruction Encoding for a 16-bit Embedded Processor with Dynamic Implied Addressing Mode, International Symposium on Advances of High Performance Computing and Network (AHPCN), 2009

  • Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), March 2009

  • Hiding Cache Miss Penalty Using Priority-based Execution for Embedded processors, Design Automation and Test in Europe (DATE), March 2008

  • Register File Power Reduction Using Bypass Sensitive Compiler, IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), 2008

  • Automatic Design Space Exploration of Register Bypasses in Embedded Processors, IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), 2007

  • HW/SW co-design for embedded system using UML, International Conference on Ubiquitous Information Technologies & Applications (ICUT), December 2007

  • Power-conscious Configuration Cache Structure and Code Mapping for Coarse-grained Reconfigurable Architecture, International Symposium on Low Power Electronics Design (ISLPED), October 2006

  • Bypass Aware Instruction Scheduling for Register File Power Reduction, ACM SIGPLAN conference on Languages, Compilers, Tests of Embedded Systems, June 2006 ( Best paper, invited for ACM Transactions on Embedded Computing Systems)

  • Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors, Design Automation and Test in Europe (DATE) 2006