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Retargetable Compiler for Embedded Processors

  • Iterative Algorithm for Compound Instruction Selection with Register Coalescing, 12th Euromicro conference on Digital System Design (DSD), Aug. 2009

  • Methodology for the efficient use of operands in the design of compound instructions in ASIP, International SoC Design Conference (ISOCC), 2009

  • SoarGen : A retargetable compiler based on Architecture Description Language and its application on a fixed point audio codec, Asia and South Pacific Design Automation Conference (ASP-DAC), January 2009

  • Register Coalescing Techniques for Heterogeneous Register Architectures, ACM Transactions on Embedded Computing Systems (TECS), January 2009

  • A code-generator generator for multi-output instructions, The International Conference on Hardware-Software Codesign and System Synthesis(CODES+ISSS), Oct. 2007

  • Fast Code Generation for Embedded Processors Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers, Transactions on High Performance Architecture and Compilation, 2007

  • Optimistic Coalescing for Heterogeneous Register Architectures, ACM Conference on Languages, Compilers and Tools for Embedded Systems or ACM SIGPLAN Notice, June 2007 ( Best paper)

  • A code generation strategy for heterogeneous register architectures, Workshop on Interaction between Compiler and Architecture (Interact), 2007

  • Using a retargetable compiler to find an optimal instruction-set for fixed-point audio codec, International SoC Design Conference, October 2005

  • A new ADL based compiler for embedded processor design, International SoC Design Conference, October 2005

  • A Quantitative Comparison of Two Retargetable Compilation Approaches, International Conference on Parallel Processing (ICPP-03), October 2003

  • Cases Studies on Automatic Extraction of Architectural Parameters in Complex Code Generation, Software and Compilers for Embedded Systems (SCOPES), also appear in Lecture Notes in Computer Science, September 2003

  • Experience with a Retargetable Compiler for a Commercial Network Processor, International Conference on Compiler, Architecture and Synthesis for Embedded Systems (CASES), October 2002

  • The Very Portable Optimizer for Digital Signal Processors, International Conference on Compiler, Architecture and Synthesis for Embedded Systems (CASES), November 2001